1. Field of the Invention
The present invention relates to a semiconductor memory device and a writing control method thereof, and, more particularly relates to a semiconductor memory device having a memory cell of which a required time of writing data is relatively long, and a writing control method of such a semiconductor memory device.
2. Description of Related Art
In personal computers or servers, hierarchically constructed various storage devices are used. A lower-hierarchical storage device is required to be low price and has a large capacity, while a higher-hierarchical one is required to be capable of high-speed access. As a lowest-hierarchical storage device, a magnetic storage such as a hard disk drive and a magnetic tape is generally used. The magnetic storage is nonvolatile and capable of saving a considerably large amount of data at a lower price as compared to a semiconductor memory device or the like. However, the magnetic storage is slow in access speed, and does not have random accessibility in many cases. Therefore, a program or data to be saved for a long period is stored in the magnetic storage, and is optionally changed to a higher-hierarchical storage device.
A main memory is a storage device higher in hierarchy than the magnetic storage. Generally, a DRAM (Dynamic Random Access Memory) is used for the main memory. The DRAM can be accessed at higher speed as compared to the magnetic storage, and in addition, the DRAM has the random accessibility. Further, the DRAM has a characteristic that a cost-per-bit is lower in price than a high-speed semiconductor memory such as an SRAM (Static Random Access Memory).
A highest-hierarchical storage device is an internal cache memory included in an MPU (Micro Processing Unit). The internal cache memory is connected via an internal bus to a core of the MPU, and thus, it can be accessed at remarkably high speed. However, a recording capacity to be secured is considerably small. As a storage device that configures a hierarchy between the internal cache and the main memory, a secondary cache, or a tertiary cache, or the like is used occasionally.
The reason that the DRAM is selected as the main memory is that it has a very good balance between the access speed and the cost-per-bit. Further, the DRAM has a large capacity among the semiconductor memories, and recently, a chip with a capacity of 1 gigabit or more has been developed. However, the DRAM is a volatile memory, and stored data is lost when the power is turned off. Thus, the DRAM is not suitable for a program or data to be save for a long period. In the DRAM, a refresh operation needs to be periodically performed to save the data even while the power supply is turned on. Thus, there is a limit to reduction in power consumption, and there is a problem that complicated control by a controller is needed.
As a nonvolatile semiconductor memory of large capacity, a flash memory is known. However, the flash memory has disadvantages in that a large amount of electricity is needed to write and delete the data, and a writing time and a deleting time are very long. Accordingly, it is not appropriate to replace the DRAM as the main memory. Other nonvolatile memories that have been proposed include an MRAM (Magnetoresistive Random Access Memory), an FRAM (Ferroelectric Random Access memory) or the like. However, it is difficult to obtain a storage capacity equal to that of the DRAM.
On the other hand, as a semiconductor memory that replaces the DRAM, a PRAM (Phase change Random Access Memory) in which a phase change material is used to record is proposed (see Japanese Patent Application Laid Open Nos. 2006-24355 and 2005-158199, and U.S. Pat. No. 5,536,947). In the PRAM, the data is stored by a phase state of the phase change material included in a recording layer. That is, the phase change material differs greatly in electrical resistance between a crystalline phase and an amorphous phase. The data can be stored by using this characteristic.
The phase state can be changed by applying a write current to the phase change material, which heats the phase change material. Data-reading is performed by applying a read current to the phase change material and sensing the resistance value. The read current is set to a value sufficiently small as compared to the write current so that no phase change occurs. Thus, the phase state of the phase change material does not change unless a high heat is applied thereto, and accordingly, even when the power is turned off, the data is not lost.
To make the phase change material amorphous (the reset operation), it is necessary to heat the phase change material to a temperature equal to or higher than a melting point and to then rapidly quenching the phase change material. On the other hand, to crystallize the phase change material (the set operation), it is necessary to heat the phase change material to a temperature equal to or higher than a crystallization temperature and lower than the melting point by applying the write current to the phase change material, and to then gradually cool the phase change material. Due to this, the PRAM is characterized in that it takes longer time to perform the set operation than the reset operation.
Thus, in the PRAM, a time required for the set operation and that required for the reset operation differ greatly, and thus, to ensure compatibility with other general-purpose memory such as a DRAM, control using a set pulse for performing the set operation and a reset pulse for performing the reset operation is often performed.
On the other hand, in accessing the other general-purpose memory such as a DRAM, the address is generally inputted in twice. That is, a row address is firstly inputted, and subsequently, a column address is inputted. In the DRAM herein, for example, when the row address is inputted and thereafter different column addresses are continuously inputted, continuous data writing can be performed. To enable such a continuous data writing also in the PRAM, a write control circuit that generates the set pulse and the reset pulse (these are collectively called a write pulse) can be arranged for each page. The “page” indicates a memory cell group to which the same column address is allocated.
However, when the write control circuit is arranged for each page, a circuit size is inevitably increased. In particular, in a case of a semiconductor memory device of which the page length is long such as the DRAM, when the circuit size is increased, a chip area is greatly increased. In this regard, such a problem is generated commonly not only in the PRAM but also in a semiconductor memory device having a memory cell of which the data writing time is relatively long.